[logo] Bonus Logic Circuit

Half-Adder Circuit

[Half-Adder Circuit]

(A AND B) (A XOR B)
A: B: C: S:
(in) (in) (out) (out)
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

This circuit adds two bits: recall that the binary aritmetic of two bits is as follows:

  0 + 0 =  0
  0 + 1 =  1
  1 + 0 =  1
  1 + 1 = 10

The S output represents the sum of the two bits; in the case of 1+1 the carry bit C is set. The circuit is known as a half-adder because it ignores the possibility of a carry bit left over from a less significant bit. For example, in the following sum, the binary result 1+1+1=11 is needed, so three inputs would be needed for a full-adder.

  1011     
+ 1011
  ----
 10110

(Note that this is 11+11=22 in decimal.)


"http://www.physics.udel.edu/~watson/scen103/circuit10.html"
Last updated Dec. 9, 1996.
Copyright George Watson, Univ. of Delaware, 1996.