[logo] Digital Gate Exercise

NAND Gate
[Schematic of NAND gate]

A: B: C:
(in) (in) (out)
0 0 1
0 1 1
1 0 1
1 1 0

AND Gate
[Schematic of AND gate]

A: B: C:
(in) (in) (out)
0 0 0
0 1 0
1 0 0
1 1 1

OR Gate
[Schematic of OR gate]

A: B: C:
(in) (in) (out)
0 0 0
0 1 1
1 0 1
1 1 1

NOR Gate
[Schematic of NOR gate]

A: B: C:
(in) (in) (out)
0 0 1
0 1 0
1 0 0
1 1 0

 

Group Activity


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"http://www.physics.udel.edu/~watson/scen103/98w/gate-exer.html"
Last updated Feb. 4, 1998.
Copyright George Watson, Univ. of Delaware, 1996.