Consider the following timing diagram:
Construct the corresponding state diagram for the seven included states Q2Q1Q0.
There is one excluded state. Design a 3-bit counter circuit to force the excluded state to enter the cycle of included states at 010.
Identify the states by marking O's and 1's directly on the timing diagram.
Extract the states from the timing diagram to complete the state diagram. Make sure not to confuse the ordering 210 vs.012!
Use the flow of states in the state diagram to construct the truth table associating the Q's with the associated D's needed to get to the next state in sequence. The excluded state is associated with the desired entry state in the final row.
Find the required combination of gates via Karnaugh mapping.
|Truth Table for D2:||Truth Table for D1:||Truth Table for D0:|
|Karnaugh Map for D2:||Karnaugh Map for D1:||Karnaugh Map for D0:|
4 cyan cells: D2 = Q1
may be boxed via Q'1.Q'0
4 yellow cells: D0 = Q2
In comparison with the combination of gates originally used for Problem 4 of Chapter 14 of our text, note that Q'2.Q0 + Q2.Q'0 = Q2 XOR Q0. To fix the problem of the excluded state 000 we require that it be ORed with Q'2.Q'1.