Hint for 14.4
Hint for S14.1
Note that the starting output of each flip-flop is Q = 0 and Q' = 1.
Determine D1, D2, and D3 at the time of the positive edge of the clocking signal; find the resulting Qs for each flip-flop, then feed back two of the complemented outputs back into D1 with the AND gate.
Hint for S14.2
Going clockwise around the included states from 000, followed by going clockwise around the excluded states from 1111,
the truth table should be: