Contents
State Counters  Truth Table  Karnaugh Mapping  
Circuit Simulation  Data Sheets  Online Resources 
Objectives
Develop working knowledge of Dtype flipflops and state counters.
Exercise ability to construct truth tables and Karnaugh maps.
Gain additional experience with DeMorgan's theorems and optimization of gates.
Gain familiarity with integrated circuit data sheets.
State Counters with EWB
The objective of this lab exercise is to design, simulate, assemble, and debug a working
3bit counter that will sequence through the prime numbers between zero and eight.
The desired sequence is 2, 3, 5, and 7; that is, 010, 011, 101, and 111.
The counting sequence is generally represented in the following way with a state diagram:
In general, a 3bit counter is capable of representing eight different states; only four have been selected as allowed states for the desired counter circuit. Hence there are four excluded states; these are 000, 001, 100, and 110. Since it is possible that the counter may start up in one of the excluded states, particularly 000 in Electronics Workbench, a provision must be made to move from an excluded state to an allowed state so that the counting sequence is entered smoothly. For this lab exercise it is recommended that all excluded states be moved into the state 111, as shown:
Truth Table
Construct the truth table for the 3bit counter executing the prime number counting sequenc
described above. There should be three "inputs" Q_{1}, Q_{2}, and Q_{3}
and three "outputs" D_{1}, D_{2}, and D_{3}.
That is, construct the truth table so that the flipflop data inputs for the succeeding state
are derived from the current state.
Do NOT bother with an enable input. This will add substantial complexity to the mapping and circuit implementation.
Q_{3}  Q_{2}  Q_{1}  D_{3}  D_{2}  D_{1}  

0  1  0  
0  1  1  
1  0  1  
1  1  1  
0  0  0  
0  0  1  
1  0  0  
1  1  0 



Derive the Boolean expression for each of the D's involving ANDs and ORs among the flipflop Qs and Q's.
Conmplete the timing diagram below, showing the progression of the four states through two complete cycles, starting from 111.
Use this standalone Timing Diagram Grid if you prefer.
Retain a printed copy of the circuit diagram as this will serve for next week's laboratory exercise  actual IC realization of the 3bit Prime Number Counter. Finally real ICs...
Data Sheets
Integrated circuit packages available in the lab next week will include
Relevant Online Resources
74HCT Digital ICs,
listing from RadioShack
Includes some Motorola, National Semiconductor, and Texas Instruments data sheets.
74HCT00, Quad 2Input NAND Gate
74HCT00, Quad 2Input NOR Gate
74HCT74, Dual DType FlipFlop
74HCT175, Quad DType FlipFlop
Logic Data Sheets from
Harris Semiconductor
Logic ICs
from Motorola
Logic Products
from Texas Instruments
Digikey, retailer of electronics parts