## PHYS345 Electricity and Electronics

Sequential Logic with

Contents

Objectives
Develop working knowledge of D-type flip-flops and state counters.
Exercise ability to construct truth tables and Karnaugh maps.
Gain additional experience with DeMorgan's theorems and optimization of gates.
Gain familiarity with integrated circuit data sheets.

State Counters with EWB
The objective of this lab exercise is to design, simulate, assemble, and debug a working 3-bit counter that will sequence through the prime numbers between zero and eight. The desired sequence is 2, 3, 5, and 7; that is, 010, 011, 101, and 111. The counting sequence is generally represented in the following way with a state diagram:

In general, a 3-bit counter is capable of representing eight different states; only four have been selected as allowed states for the desired counter circuit. Hence there are four excluded states; these are 000, 001, 100, and 110. Since it is possible that the counter may start up in one of the excluded states, particularly 000 in Electronics Workbench, a provision must be made to move from an excluded state to an allowed state so that the counting sequence is entered smoothly. For this lab exercise it is recommended that all excluded states be moved into the state 111, as shown:

Truth Table
Construct the truth table for the 3-bit counter executing the prime number counting sequenc described above. There should be three "inputs" Q1, Q2, and Q3 and three "outputs" D1, D2, and D3. That is, construct the truth table so that the flip-flop data inputs for the succeeding state are derived from the current state.

Do NOT bother with an enable input. This will add substantial complexity to the mapping and circuit implementation.

Q3 Q2 Q1   D3 D2 D1
0 1 0
0 1 1
1 0 1
1 1 1

0 0 0
0 0 1
1 0 0
1 1 0

Karnaugh Mapping
Construct the Karnaugh map for each of the D inputs. Following this it should be clear why it was suggested that 111 be the entry state for the excluded states.

D3Q1 0  1
Q3Q2\
00
01
11
10

D2Q1 0  1
Q3Q2\
00
01
11
10

D1Q1 0  1
Q3Q2\
00
01
11
10

Derive the Boolean expression for each of the D's involving ANDs and ORs among the flip-flop Qs and Q's.

1. Using the Boolean expressions from the Karnaugh mapping, use Electronics Workbench to assemble the 3-bit Prime Number Counter using D flip-flops along with AND and OR gates. Confirm the correct counting sequence and show your working circuit to the laboratory instructor when ready.

Conmplete the timing diagram below, showing the progression of the four states through two complete cycles, starting from 111.

Use this standalone Timing Diagram Grid if you prefer.

2. Convert the gate combinations to all NAND gates by application of DeMorgan's theorems. If you prefer, you may choose to use all NOR gates instead.

3. Assemble a working model of the integrated circuit solution to the desired state counter. Confirm the correct counting sequence and show your working circuit to the laboratory instructor when ready.

Retain a printed copy of the circuit diagram as this will serve for next week's laboratory exercise -- actual IC realization of the 3-bit Prime Number Counter. Finally real ICs...

Data Sheets
Integrated circuit packages available in the lab next week will include

Relevant Online Resources
74HCT Digital ICs, listing from RadioShack
Includes some Motorola, National Semiconductor, and Texas Instruments data sheets.