PHYS345 PHYS345 Class 18

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Introduction to Sequential Logic

Gates and Timing Diagrams
    Simple Gating Circuit for EWB
    Simple Multiplexing Circuit

    Timing Diagram Template


D flip-flop
    JK flip-flop

(not studied
in PHYS345)

    Demonstration of D flip-flop


    Toggle flip-flop
    4-bit ripple counter
    Human 4-bit ripple counter and intermediate states

State Machines: A Case Study
2-bit counter with states 00, 01, 11, and 10 in sequence
    Truth Table
    Karnaugh Map
    Circuit Realized from Karnaugh Mapping
    Circuit Realized with NANDs and D FFs
    Circuit Realized with Actual ICs

Additional Online Resources
    Sequential Logic, from the Digital Logic/Play-Hookey Website

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Last updated November 11, 1998.
Copyright George Watson, Univ. of Delaware, 1998.