## PHYS345 Electricity and Electronics

Quiz 9: Sequential Logic

Consider this state counter constructed from D flip-flops and OR gates. The two flip-flops are clocked simultaneously with the same CLK.

Complete enough of the timing diagram below to determine the sequence of states that are accessed (allowed) by this counter. Start with all Qs=0 as shown.

Comment on excluded states (if any) and indicate the point of entry into the counting sequence on a state diagram.

The OR gate for FF1 is setting up Q'1+Q'2. The OR gate for FF2 is setting up Q1+Q'2.

From each combinations of Qs, the Ds are set up for the next transition as follows:

The state diagram for this counter is:

The excluded state is (00); if the counter starts in that state for some reason, it will go to the state (11), otherwise (00) is never allowed. The sequence (11),(10),(01) is repeated, so I call this a 3-2-1 counter.

"http://www.physics.udel.edu/~watson/phys345/quiz/9soln.html"
Last updated Nov. 19, 1998.
Copyright George Watson, Univ. of Delaware, 1998.