PHYS345 Electricity and Electronics

Quiz 9: Sequential Logic

Consider this state counter constructed from D flip-flops and OR gates. The two flip-flops are clocked simultaneously with the same CLK.

2-bit state counter

Complete enough of the timing diagram below to determine the sequence of states that are accessed (allowed) by this counter. Start with all Qs=0 as shown.

Timing diagram template

Comment on excluded states (if any) and indicate the point of entry into the counting sequence on a state diagram.


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Last updated Nov. 19, 1998.
Copyright George Watson, Univ. of Delaware, 1998.