## PHYS345 Electricity and Electronics

Timing Diagram Template

Note that the starting output of each flip-flop is Q = 0 and Q' = 1. The data label for the second flip-flop should be D2, not D1.

Determine D1, D2, and D3 at the time of the positive edge of the clocking signal; find the resulting Qs for each flip-flop, then feed two of the complemented outputs back into D1 with the AND gate.

The starting output of each flip-flop is Q = 0 and Q' = 1.

Determine the Ds at the time of the positive edge of the clocking signal; find the resulting Qs for each flip-flop, then feed two of the complemented outputs back into the first D input with the OR gate.

Determine how one row of D's leads to the next row of Q's in the truth table - remember that this is sequential logic. You may study Table 9.1 in the textbook which is a truth table for a different counter.

Note also that there are four inputs: the enable bit E and the three data bits, D1, D2, and D3. There are three outputs: Q1, Q2, and Q3, not four as claimed in the last sentence of the problem statement. The objective is to derive the D's for the subsequent state from the Q's for the current state.

Construct Karnaugh mapping of EQ3\Q2Q1 to find the combination of gates needed to derive the D's from the Q's, similar to the process on pg. 253 of the textbook.

This is an extension of the timing diagram that was presented in the class on sequential logic.

"http://www.physics.udel.edu/~watson/phys345/protected/exercises/hints/1105.html"
Last updated Nov. 9, 1998.
Copyright George Watson, Univ. of Delaware, 1998.