## PHYS345 Electricity and Electronics

**Timing Diagram Template**
**Hint for P9.13**

Note that the starting output of each flip-flop is Q = 0
and Q' = 1. The data label for the second flip-flop should
be D_{2}, not D_{1}.

Determine D_{1}, D_{2}, and D_{3} at
the time of the positive edge of the clocking signal; find the resulting
Qs for each flip-flop, then feed two of the complemented outputs
back into D_{1} with the AND gate.

**Hint for P9.15**

The starting output of each flip-flop is Q = 0
and Q' = 1.

Determine the Ds at
the time of the positive edge of the clocking signal; find the resulting
Qs for each flip-flop, then feed two of the complemented outputs
back into the first D input with the OR gate.

**Hint for P9.21**

Determine how one row of D's leads to the next row of Q's in the truth table -
remember that this is *sequential* logic. You may study Table 9.1 in the textbook
which is a truth table for a different counter.

Note also that there are four inputs: the enable bit E and the three data bits, D_{1},
D_{2}, and D_{3}. There are three outputs: Q_{1},
Q_{2}, and Q_{3}, not four as claimed in the last sentence of the problem statement.
The objective is to derive the D's for the subsequent state from the Q's for the current state.

Construct Karnaugh mapping of EQ_{3}\Q_{2}Q_{1}
to find the combination of gates needed to derive the D's from the Q's,
similar to the process on pg. 253 of the textbook.

**Hint for P9.22**

This is an extension of the timing diagram that was presented in the class
on sequential logic.

"http://www.physics.udel.edu/~watson/phys345/protected/exercises/hints/1105.html"

Last updated Nov. 9, 1998.

Copyright George Watson, Univ. of Delaware, 1998.